module top(CLOCK,reset,rst,LED,state);
input CLOCK,reset,rst;
output [11:0] LED;
output [1:0]state;
wire clk_out;
div u1(.clock(CLOCK),.rst(reset),.clk_out(clk_out));
ledw u2(.clk(clk_out),.led(LED),.rst(rst),.state(state));
endmodule